联系我们

与泰克代表实时聊天。 工作时间：上午 9:00 - 下午 5:00（太平洋标准时间）。

电话

致电我们

工作时间：上午9:00-下午5:00（太平洋标准时间）

下载

下载手册、产品技术资料、软件等：

下载类型
型号或关键字

反馈

Tektronix Receiver Test Automation Software for PCIe 4.0 (CEM and Base), PCIe 5.0 (CEM and Base), PCIe 6.0 (Base) , PCIe PLL Bandwidth (Gen 3/4/5), USB4 (Gen 2/3) and TBT3/4 (Gen 2/3 Legacy and Rounded)

The TekRxTest Automation Software supports PCIe 4.0 (Base and CEM), PCIe 5.0 (Base and CEM), PCIe 6.0(Base), PCIe PLL Bandwidth (Gen 3/4/5), USB4 (Gen 2/3) and TBT3/4 (Gen 2/3 Legacy and Rounded) calibration and receiver tests (Compliance & Beyond Compliance).The PCIe calibration and tests are in accordance with PCI Express Base Specification Revision 6.0, Version 1.0 and PCI Express Card Electromechanical Specification Revision 5.0, Version 1.0. The USB4 and TBT3/4 calibration and tests are in accordance with the USB4 Electrical CTS Revision 1.02.The Calibration procedure is done by connecting the output of the BERT PPG to the Real-time Oscilloscope through a specialized set of fixtures and cables. The BERT can be programmed to add different amounts of random jitter, sinusoidal jitter, differential, and common mode interference along with variable signal amplitude, preshoot, and de-emphasis and the different parameters are calibrated at two test points.The Receiver tests are accomplished by connecting the output of BERT PPG (which can produce specific test patterns) to the input of the DUT through the same set of fixtures and cables, on which the calibration was done. In case of the PCIe Receiver tests, the output of the DUT is connected to the BERT error detector to identify bit errors on the DUT Tx traffic, either during loopback or during sweep of one of the stress parameters. Any error detected can be assumed to come from the DUT Tx path as a result of either the DUT experiencing a bad bit-decision at its receiver or uncompensated back-channel loss at the error detector of the BERT. Additionally, DUT Tx traffic can be analyzed to verify the DUT responsiveness to various requests put forward by the BERT during link training process.In the case of PCIe PLL BW (Gen 3/4/5), the BERT can be programmed to add different amounts of sinusoidal jitter. Post Calibration, the output of the DUT is connected to the Real-time Oscilloscope, to measure the Transmitter DUT‚s PLL bandwidth and peaking.In case of USB4 (Gen 2/3) and TBT3/4 (Gen 2/3 Legacy and Rounded), post calibration, the output of the DUT is connected to the Wilder microcontroller to identify the bit errors on the DUT Tx traffic after preset negotiation is done using the ETT tool while sweeping one of the stress parameters.

此软件适用于： DPS75004SX, DPS75904SX, DPS77004SX, DPO73304SX, DPO73304DX

相关产品信息