Corus Validation Suite Datasheet

Features & Benefits

• Very Wide Data Capture Width with Extensive Compression to Optimize Depth
• Time-correlated View across Multiple Clock Domains and across FPGAs
• Any Observed Signal, Any Time, Avoids Frequent FPGA Re-synthesis
• Complex Triggering and Cross-triggering with Test Equipment and Software Debuggers
• Fast and Easy Capture Probe Insertion in FPGAs

Delivering Design-for-Visibility

Imagine how much faster FPGA system validation and debug would be if you were able to see a time-correlated view of all of your system, not only serial I/O, buses, and software code, but inside the FPGAs as well. The Corus FPGA Systems Validation Suite restores internal visibility by addressing these limitations up-front in the design phase. Corus enables true Design-for-Visibility.

Embedded systems design instruments are fundamental to Design-for-Visibility. Embedded instruments must:

• Scale with technology
• Leverage the same trends that are driving complexity into systems
• Run at speed within the FPGA
• Be scalable across blocks, design, chips, boards, and systems
• Be deployable across the development cycle and into final system

The Corus FPGA Systems Validation Tool Suite is the ideal Design-For-Visibility tool. Corus:

• Produces a system-wide time-correlated view
• Enables observations of large numbers (thousands) of signals
• Delivers “system-time” scale trace depths
• Is implementable across FPGA vendors and ASIC technologies

Corus is a suite of software tools and IP providing everything required to enhance visibility on-chip and off-chip. At the design stage, the easy-to-use Implementor tool applies advanced proprietary algorithms to help you design and implement minimized on-chip signal capture probes quickly and efficiently on your FPGAs.

Implementor Tool

• Automatic infrastructure generation
• OptiRank recommends signals for probing
• Automatic clock discovery
• Work from any level of design hierarchy
• FPGA resource utilization summary
• Equivalent signal identification
• Preserves RTL source names

During validation, the capture probes are managed by an Analyzer tool through the JTAG port. Complex and cross triggers are easily set up. The Corus “any signal, any time” feature avoids seemingly endless re-synthesis when selecting signals. The resulting highly compressed captures are processed off-chip by proprietary algorithms that recreate the internal chip data and re-synchronize the captures from different clock domains and FPGAs into one view.

Corus can be used with Xilinx, Altera, or Actel FPGAs and requires no special I/O, connectors, or FPGA topology. Simple JTAG connectivity allows full synchronized debug across FPGAs.